1. Field of the Invention
The present invention relates generally to circuit detecting a phase difference between two pulse signals in any phase relation, and more particularly, to a pulse phase difference encoding circuit capable of detecting the phase difference with high precision over a wide range.
2. Description of Related Art
A pulse phase difference encoding circuit designed to convert a phase difference (or a time difference) between two pulse signals into a code (or a numerical value) has been disclosed in, for example, U.S. Pat. No. 5,128,624 to Hoshino et al. This conventional pulse phase difference encoding gate includes delay elements comprising a ringed connection of a NAND circuit and a plurality of inverters, circulates a first pulse signal inputted therein at any timing through the ringed connection, counts the number of such circulations on one hand, and specifies the position of the circulation of the first pulse signal in the ringed connection at a timing of the input of a second pulse signal on the other hand, and detects the phase difference between the two pulse signals based on the specified position and the counted number of circulations. However, the above conventional pulse phase difference encoding circuit has the following problems.
Firstly, a ring delay pulse generating circuit having the ringed connection of the plurality of delay elements connects the output from the delay element in the last stage to the delay element in the first stage with a signal line (i.e. a conductive strip in an integrated circuit) to complete the ring. When the signal line connecting the delay element in the last stage to the delay element in the first stage (hereinafter referred to as the "B signal line") and the signal lines connecting the other delay elements to each other (hereinafter referred to as "A signal lines") are compared with each other, the A signal lines may become longer than the B signal line in some cases.
For example, as seen in the circuit layout diagram of the ring delay pulse generating circuit illustrated in FIG. 13, when a plurality of D-type flip-flops (hereinafter referred to as "DFFs") forming a pulse selector 20 are laid out within the ringed wiring of the NAND gate and inverters IN1 through IN62 each of which serves as a delay elements of the pulse phase difference encoding circuit, a difference occurs in the lengths between the signal line A connecting the straight portion through a plurality of delay elements from the first stage, the signal line B1 connecting the turn portion between the inverter IN31 in the intermediate portion of the ring and the inverter IN32 in the intermediate portion of the ring, and the signal line B2 connecting the turn portion between the last inverter IN62 and the NAND circuit.
In the above arrangement, assuming the signal lines have a uniform line width, the load capacitance of the signal lines B1 and B2 are larger than the load capacitance of the signal line A, and as a result, the delay time in the pulse phase difference encoding circuit is uneven. Consequently, as illustrated in FIG. 14, a difference occurs in time resolutions a, b1 and b2 (representing a digital output value from, e.g., inverter IN1, digital output value of "31" corresponding to the signal line B1 between the inverters IN31 and IN32, and a digital output value of "62" corresponding to the signal line B2 between the inverter IN62 and the NAND gate, respectively), and the time resolutions are thereby degraded. In this case, the time resolutions a, b1 and b2 illustrated in FIG. 14 are determined by the dimensions of the signal lines A, B1 and B2, respectively. Furthermore, the load capacitance of the signal lines are proportional to the widths and lengths of the signal lines. In FIG. 14, however, the widths of the signal lines are assumed to be equal to each other, and only the lengths thereof are assumed to be different from each other.
Secondly, the above conventional pulse phase difference encoding circuit uses the NAND gate and the inverters IN as delay elements forming a ring delay pulse generating circuit. Normally, however, since the switching speed of the NAND gate is slower than that of the inverters IN, a difference in the signal delay speed is caused, and the time resolutions are uneven.
Thirdly, the above conventional pulse phase difference encoding circuit is responsive to latch pulses driving the pulse selector and the counter DFF. Normally, the second pulse signal PB is inputted into a pulse selector and a counter DFF through a buffer. In many practical applications, however, as illustrated in FIG. 16, latch pulses PB1 for the pulse selector and clock pulses for driving the DFFs in the other blocks, such as a digital filter 101A and a digital comparator 102A, are all output signals from the buffer 90. That is, the buffer 90 for the latch pulses of the pulse selector drives the other circuits as well. For this reason, the buffer 90 has a large loading capacitance, and as a result, the transition of PB1 between logic levels is not steep and the measurements are uneven.
Fourthly, the above conventional pulse phase difference encoding circuit has no measures to counter a case where the measurement time exceeds the upper limits of the measurement range (overflow) or aberrations where the second pulse signal is inputted prior to the input of the first pulse signal (underflow), both cases being expected when the conventional pulse phase difference encoding circuit is used in connection with a sensor. Therefore, as illustrated in FIG. 15, the digital outputs are uneven.